Memory in SPARC Machines

SPARC, like all modern computers, is based on the von Neumann architecture, which has an addressable memory in which both instructions and data are stored.

It is rare for a program to need access to an individual bit in memory all by itself; instead, programs usually require access to some number of bits stored consecutively in memory. So there are significant cost and speed advantages to designing an architecture which:

• Provides fast access to a number of consecutive bits simultaneously, to make common operations as fast as possible;
• Does not provide access to individual bits one at a time, since cost can be reduced by not implementing this rare operation directly (either that money can be saved or it can be spent on some other feature of greater use; you can always get ahold of an individual bit if necessary by reading, say, a whole byte containing that particular bit).

• 1 byte = 8 bits
• 1 halfword = 2 bytes = 16 bits
• 1 word = 4 bytes = 32 bits
• 1 double word = 2 words = 8 bytes = 64 bits

Each location in memory holds one byte (8 bits) of data; each location is identified by its own unique address (a 32-bit unsigned integer).

You can also use an address to refer to one of the larger units of memory (halfword, word, or double word). In this case, the address refers to the first byte of the 2, 4, or 8 consecutive bytes involved. For the sake of efficiency, the SPARC architecture requires that you make sure that all memory references are aligned; in other words, a halfword must start at an even memory address, a word must start at an address which is a multiple of 4, and a double word must start at an address which is a multiple of 8.

SPARC is a big-endian architecture. This means that multi-byte quantities (halfword, word, or double word) are stored with their most significant byte first (in the lowest address) and their least significant byte last (in the highest address). For example, if you stored the number 256 (binary 100000000) as a word at location 500, you would find the byte 1 stored at location 500, and the byte 0 stored at location 501.

Little-endian architectures store multi-byte quantities in the opposite order, with the least significant byte first. It doesn't really matter which method is used, but you do need to be aware of the order in a few situations (whether programming in assembly language or in a high-level language):

• You refer to the same value in two different ways; for example, you take a word and handle its four individual bytes separately.
• You take raw data values and send them from a big-endian computer to a little-endian one (or vice versa), either via a file or via a network.
• You are writing a program that you intend to be portable between different architectures; in this case, you need to carefully avoid or isolate any dependencies on endian-ness.

Of the common microprocessors, the Motorola 680x0 series has a big-endian architecture, like SPARC. Intel microprocessors are little-endian. PowerPC processors can be configured either way; the most common machines using them are big-endian.

The terms big-endian and little-endian come from Jonathan Swift's Gulliver's Travels, in which politicians argued and nations made war over which side of an egg should be cracked open.