Program Counters, Pipelining,
and the Delay Slot

A typical microprocessor has a program counter, a special register holding the address of the instruction currently being executed. As part of executing an instruction, this program counter is automatically advanced to point to the next instruction; in the case of a jump, subroutine call, etc., a new value will simply be loaded into the program counter in order to cause a jump in the flow of control.

SPARC is a RISC (reduced instruction set computing) architecture, in which instructions are pipelined for greater speed. This means that consecutively-executing instructions can have their execution overlapped in time. The details of instruction execution are arranged so that the CPU doesn't have to wait for one operation to finish before starting the next.

The way this pipelining is visible to the programmer is via overlapping of the fetch-execute cycle. When the CPU is ready to execute an instruction, it must first fetch that instruction (asking memory to retrieve the instruction at the appropriate address) and then execute that instruction (figuring out which operation is specified by that instruction and actually carrying it out).

In the SPARC architecture, at any given time, the CPU will be executing some instruction and, at the same time, it will be fetching the next instruction in the program. To implement this, the CPU contains two program counter registers:

• The program counter, %pc, holds the address of the instruction which is currently being executed.
• The next program counter, %npc, holds the address of the instruction which is currently being fetched and which will be executed next.

After an instruction is executed, the CPU copies the value of %npc into %pc, so that the instruction that was just fetched is now executed. Also, the value of %npc is normally incremented by 4 so that it points to the next instruction to be fetched (each SPARC instruction is 4 bytes, or 1 word, long).

If a transfer instruction is executed (one that causes a jump in flow of control, for example, a subroutine call or return, or a jump or branch instruction), the %npc register is loaded with a new value to cause the processor to jump out-of-sequence when it fetches the next instruction.

Notice that when there is a jump in the flow of control (a subroutine call, etc.), causing %npc to be loaded with the address of the instruction you want to jump to, there already is an instruction in the pipeline. The instruction in the pipeline is the instruction that was fetched at the same time the transfer instruction was being executed; this is the instruction appearing immediately after the call or jump in the code. This instruction is said to be in the call or jump's delay slot.

A natural approach might be simply to discard the instruction in the delay slot. After all, it has only been fetched at this point, not yet executed, so it could be discarded with no harm done. Unfortunately, this approach would slow the computer down considerably, since the time spent in fetching instructions that are then discarded would be wasted. So this is not what SPARC machines do.

Instead, the instruction in the delay slot, which is already in the pipeline, will be executed before the processor actually has a chance to jump to the new location. This is the simplest scheme for the chip designer to implement, since the general pipelining mechanism can be used without making any exceptions for transfer instructions; and it is the fastest way of arranging things, since no instructions are discarded.

The SPARC assembly language programmer must be aware of delay slots constantly while coding any change in flow of control, since the order of instruction execution is reversed from the order in which the instructions appear.