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The Processor State Register
Condition Codes

For more, see: SPARC at Enchanted Learning

The processor state register (PSR) is a one-word register used to keep track of various aspects of the state of the CPU that are not stored elsewhere. It is composed of a number of bit fields, which are simply located together for convenience in a single 32-bit register.

The following table describes briefly the various bit fields comprising the PSR.

Bit numbers Field name Description
31:24 Reserved
23:20 icc Integer condition codes: one bit each for N, Z, V, and C (negative, zero, overflow, and carry)
19:13 Reserved
12 EF Set if a floating-point coprocessor is available
11:8 PIL Processor interrupt level
7 S Set if the processor is in supervisor mode; clear if it is in user mode
6 PS Value of S bit when the most recent trap occurred
5 ET Set if traps are enabled (which is when the machine is not currently in a trap)
4:0 CWP Current window pointer. Keeps track of which "register set" (output, local, and input registers) is currently in use. The save instruction decrements CWP, and the restore instruction increments CWP.

Condition Codes

The most important bits in the PSR are the condition codes N, Z, V, and C.

The bits N, Z, V, and C are set and cleared as side-effects of various instructions. Your program can test a condition code bit and conditionally branch to another instruction only if that bit is 0 or only if that bit is 1. This is the assembly-language version of the if-then statement.

The carry bit C can also be used in implementing addition and subtraction of integers longer than 32 bits.

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