SPARC Architecture

SPARC is a fast architecture based on reduced-instruction set computing (RISC). It is found primarily on computers made by Sun Microsystems, Inc.

SPARC uses a load-store architecture, meaning all calculations are performed on registers in the central processing unit (CPU); load and store instructions separate from the calculations must be used in order to read data from memory into CPU registers and to store data in memory from CPU registers.

This page summarizes SPARC architecture, meaning the fundamental hardware components of a SPARC machine together with their basic functioning and interaction.

We will need to look both at the CPU and at memory. These form the heart of any computer system, with input/output devices and other peripherals added on but not affecting basic operation.

• Memory
• Integer Registers
• Two Program Counters, Pipelining, and the Delay Slot
• The Processor State Register and Condition Codes
• Multiply/Divide Register Y
• Window Invalid Mask Register WIM
• Trap Base Register TBR
• Floating-Point Coprocessor